Power Step 2 Registers Settings

Settings for registers of Power Step 2 Click driver. More...

Macros
#define	POWERSTEP2_GEN_ABS_POS_HOME   0x000000ul
	Power Step 2 parameter register settings.
#define	POWERSTEP2_GEN_ABS_POS_MASK   0x3FFFFFul
#define	POWERSTEP2_GEN_EL_POS_STEP_ZERO   0x0000
#define	POWERSTEP2_GEN_EL_POS_STEP_MASK   0x0180
#define	POWERSTEP2_GEN_EL_POS_MICROSTEP_ZERO   0x0000
#define	POWERSTEP2_GEN_EL_POS_MICROSTEP_MASK   0x007F
#define	POWERSTEP2_GEN_EL_POS_MASK   0x01FF
#define	POWERSTEP2_GEN_MARK_ZERO   0x000000ul
#define	POWERSTEP2_GEN_MARK_MASK   0x3FFFFFul
#define	POWERSTEP2_GEN_SPEED_MASK   0x0FFFFFul
#define	POWERSTEP2_GEN_ACC_14_55_STEP_S2   0x0001
#define	POWERSTEP2_GEN_ACC_29_1_STEP_S2   0x0002
#define	POWERSTEP2_GEN_ACC_101_85_STEP_S2   0x0007
#define	POWERSTEP2_GEN_ACC_1004_STEP_S2   0x0045
#define	POWERSTEP2_GEN_ACC_1004_STEP_S2   0x0045
#define	POWERSTEP2_GEN_ACC_2008_STEP_S2   0x008A
#define	POWERSTEP2_GEN_ACC_59575_541_STEP_S2   0x0FFF
#define	POWERSTEP2_GEN_ACC_MASK   0x0FFF
#define	POWERSTEP2_GEN_DEC_14_55_STEP_S2   0x0001
#define	POWERSTEP2_GEN_DEC_29_1_STEP_S2   0x0002
#define	POWERSTEP2_GEN_DEC_101_85_STEP_S2   0x0007
#define	POWERSTEP2_GEN_DEC_1004_STEP_S2   0x0045
#define	POWERSTEP2_GEN_DEC_2008_STEP_S2   0x008A
#define	POWERSTEP2_GEN_DEC_59575_541_STEP_S2   0x0FFF
#define	POWERSTEP2_GEN_DEC_MASK   0x0FFF
#define	POWERSTEP2_GEN_MAX_SPEED_15_25_STEP_S   0x0001
#define	POWERSTEP2_GEN_MAX_SPEED_30_5_STEP_S   0x0002
#define	POWERSTEP2_GEN_MAX_SPEED_305_STEP_S   0x0014
#define	POWERSTEP2_GEN_MAX_SPEED_991_25_STEP_S   0x0041
#define	POWERSTEP2_GEN_MAX_SPEED_15610_STEP_S   0x03FF
#define	POWERSTEP2_GEN_MAX_SPEED_MASK   0x03FF
#define	POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_LOW   0x0000
#define	POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_HIGH   0x1000
#define	POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_MASK   0x1000
#define	POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_STEP_S   0x0000
#define	POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_238_STEP_S   0x0001
#define	POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_476_STEP_S   0x0002
#define	POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_2_38_STEP_S   0x000A
#define	POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_976_3_STEP_S   0x0FFF
#define	POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_MASK   0x0FFF
#define	POWERSTEP2_GEN_MIN_SPEED_MASK   0x1FFF
#define	POWERSTEP2_GEN_ADC_OUT_MASK   0x1F
#define	POWERSTEP2_GEN_OCD_TH_31_25_MV   0x00
#define	POWERSTEP2_GEN_OCD_TH_62_5_MV   0x01
#define	POWERSTEP2_GEN_OCD_TH_93_75_MV   0x02
#define	POWERSTEP2_GEN_OCD_TH_281_25_MV   0x08
#define	POWERSTEP2_GEN_OCD_TH_531_25_MV   0x10
#define	POWERSTEP2_GEN_OCD_TH_1000_MV   0x1F
#define	POWERSTEP2_GEN_OCD_TH_MASK   0x1F
#define	POWERSTEP2_GEN_FS_SPD_BOOST_MODE_DISABLE   0x0000
#define	POWERSTEP2_GEN_FS_SPD_BOOST_MODE_ENABLE   0x0400
#define	POWERSTEP2_GEN_FS_SPD_BOOST_MODE_MASK   0x0400
#define	POWERSTEP2_GEN_FS_SPD_FS_SPD_7_63_STEP_S   0x0000
#define	POWERSTEP2_GEN_FS_SPD_FS_SPD_22_88_STEP_S   0x0001
#define	POWERSTEP2_GEN_FS_SPD_FS_SPD_38_13_STEP_S   0x0002
#define	POWERSTEP2_GEN_FS_SPD_FS_SPD_15617_STEP_S   0x03FF
#define	POWERSTEP2_GEN_FS_SPD_FS_SPD_MASK   0x03FF
#define	POWERSTEP2_GEN_FS_SPD_MASK   0x07FF
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_EN_DISABLE   0x00
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_EN_ENABLE   0x80
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_EN_MASK   0x80
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_FULL_STEP   0x00
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_HALF_STEP   0x10
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_QUARTER_STEP   0x20
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_8   0x30
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_16   0x40
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_32   0x50
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_64   0x60
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_128   0x70
#define	POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_MASK   0x70
#define	POWERSTEP2_GEN_STEP_MODE_CM_VM_VOLTAGE   0x00
#define	POWERSTEP2_GEN_STEP_MODE_CM_VM_CURRENT   0x08
#define	POWERSTEP2_GEN_STEP_MODE_CM_VM_MASK   0x08
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_FULL_STEP   0x00
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_HALF_STEP   0x01
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_QUARTER_STEP   0x02
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_8   0x03
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_16   0x04
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_32   0x05
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_64   0x06
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_128   0x07
#define	POWERSTEP2_GEN_STEP_MODE_STEP_SEL_MASK   0x07
#define	POWERSTEP2_GEN_STEP_MODE_MASK   0xFF
#define	POWERSTEP2_GEN_ALARM_EN_CMD_ERROR_MASK   0x80
#define	POWERSTEP2_GEN_ALARM_EN_SW_ON_MASK   0x40
#define	POWERSTEP2_GEN_ALARM_EN_STALL_DET_MASK   0x20
#define	POWERSTEP2_GEN_ALARM_EN_ADC_UVLO_MASK   0x10
#define	POWERSTEP2_GEN_ALARM_EN_UVLO_MASK   0x08
#define	POWERSTEP2_GEN_ALARM_EN_THERMAL_WARN_MASK   0x04
#define	POWERSTEP2_GEN_ALARM_EN_THERMAL_SD_MASK   0x02
#define	POWERSTEP2_GEN_ALARM_EN_OVERCURRENT_MASK   0x01
#define	POWERSTEP2_GEN_ALARM_EN_MASK   0xFF
#define	POWERSTEP2_GEN_GATECFG1_WD_EN_DISABLE   0x0000
#define	POWERSTEP2_GEN_GATECFG1_WD_EN_ENABLE   0x0800
#define	POWERSTEP2_GEN_GATECFG1_WD_EN_MASK   0x0800
#define	POWERSTEP2_GEN_GATECFG1_TBOOST_0_NS   0x0000
#define	POWERSTEP2_GEN_GATECFG1_TBOOST_62_5_NS   0x0100
#define	POWERSTEP2_GEN_GATECFG1_TBOOST_1000_NS   0x0700
#define	POWERSTEP2_GEN_GATECFG1_TBOOST_MASK   0x0700
#define	POWERSTEP2_GEN_GATECFG1_IGATE_4_MA   0x0020
#define	POWERSTEP2_GEN_GATECFG1_IGATE_8_MA   0x0040
#define	POWERSTEP2_GEN_GATECFG1_IGATE_16_MA   0x0060
#define	POWERSTEP2_GEN_GATECFG1_IGATE_24_MA   0x0080
#define	POWERSTEP2_GEN_GATECFG1_IGATE_32_MA   0x00A0
#define	POWERSTEP2_GEN_GATECFG1_IGATE_64_MA   0x00C0
#define	POWERSTEP2_GEN_GATECFG1_IGATE_96_MA   0x00E0
#define	POWERSTEP2_GEN_GATECFG1_IGATE_MASK   0x00E0
#define	POWERSTEP2_GEN_GATECFG1_TCC_125_NS   0x0000
#define	POWERSTEP2_GEN_GATECFG1_TCC_250_NS   0x0001
#define	POWERSTEP2_GEN_GATECFG1_TCC_375_NS   0x0002
#define	POWERSTEP2_GEN_GATECFG1_TCC_500_NS   0x0003
#define	POWERSTEP2_GEN_GATECFG1_TCC_3750_NS   0x001D
#define	POWERSTEP2_GEN_GATECFG1_TCC_MASK   0x001F
#define	POWERSTEP2_GEN_GATECFG1_MASK   0x0FFF
#define	POWERSTEP2_GEN_GATECFG2_TBLANK_125_NS   0x00
#define	POWERSTEP2_GEN_GATECFG2_TBLANK_250_NS   0x20
#define	POWERSTEP2_GEN_GATECFG2_TBLANK_375_NS   0x40
#define	POWERSTEP2_GEN_GATECFG2_TBLANK_1000_NS   0xE0
#define	POWERSTEP2_GEN_GATECFG2_TBLANK_MASK   0xE0
#define	POWERSTEP2_GEN_GATECFG2_TDT_125_NS   0x00
#define	POWERSTEP2_GEN_GATECFG2_TDT_250_NS   0x01
#define	POWERSTEP2_GEN_GATECFG2_TDT_4000_NS   0x1F
#define	POWERSTEP2_GEN_GATECFG2_TDT_MASK   0x1F
#define	POWERSTEP2_GEN_GATECFG2_MASK   0xFF
#define	POWERSTEP2_GEN_STATUS_STALL_A_MASK   0x8000
#define	POWERSTEP2_GEN_STATUS_STALL_B_MASK   0x4000
#define	POWERSTEP2_GEN_STATUS_OCD_MASK   0x2000
#define	POWERSTEP2_GEN_STATUS_TH_STATUS_MASK   0x1800
#define	POWERSTEP2_GEN_STATUS_UVLO_ADC_MASK   0x0400
#define	POWERSTEP2_GEN_STATUS_UVLO_MASK   0x0200
#define	POWERSTEP2_GEN_STATUS_STCK_MOD_MASK   0x0100
#define	POWERSTEP2_GEN_STATUS_CMD_ERROR_MASK   0x0080
#define	POWERSTEP2_GEN_STATUS_MOT_STATUS_MASK   0x0060
#define	POWERSTEP2_GEN_STATUS_DIR_MASK   0x0010
#define	POWERSTEP2_GEN_STATUS_SW_EVN_MASK   0x0008
#define	POWERSTEP2_GEN_STATUS_SW_F_MASK   0x0004
#define	POWERSTEP2_GEN_STATUS_BUSY_MASK   0x0002
#define	POWERSTEP2_GEN_STATUS_HIZ_MASK   0x0001
#define	POWERSTEP2_GEN_STATUS_MASK   0xFFFF
#define	POWERSTEP2_V_KVAL_HOLD_0_VS   0x00
#define	POWERSTEP2_V_KVAL_HOLD_0_004_VS   0x01
#define	POWERSTEP2_V_KVAL_HOLD_0_008_VS   0x02
#define	POWERSTEP2_V_KVAL_HOLD_0_104_VS   0x19
#define	POWERSTEP2_V_KVAL_HOLD_0_168_VS   0x29
#define	POWERSTEP2_V_KVAL_HOLD_0_996_VS   0xFF
#define	POWERSTEP2_V_KVAL_HOLD_MASK   0xFF
#define	POWERSTEP2_V_KVAL_RUN_0_VS   0x00
#define	POWERSTEP2_V_KVAL_RUN_0_004_VS   0x01
#define	POWERSTEP2_V_KVAL_RUN_0_008_VS   0x02
#define	POWERSTEP2_V_KVAL_RUN_0_104_VS   0x19
#define	POWERSTEP2_V_KVAL_RUN_0_168_VS   0x29
#define	POWERSTEP2_V_KVAL_RUN_0_996_VS   0xFF
#define	POWERSTEP2_V_KVAL_RUN_MASK   0xFF
#define	POWERSTEP2_V_KVAL_ACC_0_VS   0x00
#define	POWERSTEP2_V_KVAL_ACC_0_004_VS   0x01
#define	POWERSTEP2_V_KVAL_ACC_0_008_VS   0x02
#define	POWERSTEP2_V_KVAL_ACC_0_104_VS   0x19
#define	POWERSTEP2_V_KVAL_ACC_0_168_VS   0x29
#define	POWERSTEP2_V_KVAL_ACC_0_996_VS   0xFF
#define	POWERSTEP2_V_KVAL_ACC_MASK   0xFF
#define	POWERSTEP2_V_KVAL_DEC_0_VS   0x00
#define	POWERSTEP2_V_KVAL_DEC_0_004_VS   0x01
#define	POWERSTEP2_V_KVAL_DEC_0_008_VS   0x02
#define	POWERSTEP2_V_KVAL_DEC_0_104_VS   0x19
#define	POWERSTEP2_V_KVAL_DEC_0_168_VS   0x29
#define	POWERSTEP2_V_KVAL_DEC_0_996_VS   0xFF
#define	POWERSTEP2_V_KVAL_DEC_MASK   0xFF
#define	POWERSTEP2_V_INT_SPEED_0_STEP_S   0x0000
#define	POWERSTEP2_V_INT_SPEED_0_0596_STEP_S   0x0001
#define	POWERSTEP2_V_INT_SPEED_0_1192_STEP_S   0x0002
#define	POWERSTEP2_V_INT_SPEED_61_5668_STEP_S   0x0408
#define	POWERSTEP2_V_INT_SPEED_976_5_STEP_S   0x3FFF
#define	POWERSTEP2_V_INT_SPEED_MASK   0x3FFF
#define	POWERSTEP2_V_ST_SLP_0   0x00
#define	POWERSTEP2_V_ST_SLP_0_000015   0x01
#define	POWERSTEP2_V_ST_SLP_0_00003   0x02
#define	POWERSTEP2_V_ST_SLP_0_000135   0x08
#define	POWERSTEP2_V_ST_SLP_0_004   0xFF
#define	POWERSTEP2_V_ST_SLP_MASK   0xFF
#define	POWERSTEP2_V_FN_SLP_ACC_0   0x00
#define	POWERSTEP2_V_FN_SLP_ACC_0_000015   0x01
#define	POWERSTEP2_V_FN_SLP_ACC_0_00003   0x02
#define	POWERSTEP2_V_FN_SLP_ACC_0_000135   0x08
#define	POWERSTEP2_V_FN_SLP_ACC_0_00063   0x29
#define	POWERSTEP2_V_FN_SLP_ACC_0_004   0xFF
#define	POWERSTEP2_V_FN_SLP_ACC_MASK   0xFF
#define	POWERSTEP2_V_FN_SLP_DEC_0   0x00
#define	POWERSTEP2_V_FN_SLP_DEC_0_000015   0x01
#define	POWERSTEP2_V_FN_SLP_DEC_0_00003   0x02
#define	POWERSTEP2_V_FN_SLP_DEC_0_000135   0x08
#define	POWERSTEP2_V_FN_SLP_DEC_0_00063   0x29
#define	POWERSTEP2_V_FN_SLP_DEC_0_004   0xFF
#define	POWERSTEP2_V_FN_SLP_DEC_MASK   0xFF
#define	POWERSTEP2_V_K_THERM_1   0x00
#define	POWERSTEP2_V_K_THERM_1_03125   0x01
#define	POWERSTEP2_V_K_THERM_1_0625   0x02
#define	POWERSTEP2_V_K_THERM_1_46875   0x0F
#define	POWERSTEP2_V_K_THERM_MASK   0x0F
#define	POWERSTEP2_V_STALL_TH_31_25_MV   0x00
#define	POWERSTEP2_V_STALL_TH_62_5_MV   0x01
#define	POWERSTEP2_V_STALL_TH_93_75_MV   0x02
#define	POWERSTEP2_V_STALL_TH_281_25_MV   0x08
#define	POWERSTEP2_V_STALL_TH_531_25_MV   0x10
#define	POWERSTEP2_V_STALL_TH_1000_MV   0x1F
#define	POWERSTEP2_V_STALL_TH_MASK   0x1F
#define	POWERSTEP2_V_CONFIG_F_PWM_INT_19_5_KHZ   0x0000
#define	POWERSTEP2_V_CONFIG_F_PWM_INT_31_3_KHZ   0x0000
#define	POWERSTEP2_V_CONFIG_F_PWM_INT_62_5_KHZ   0x0000
#define	POWERSTEP2_V_CONFIG_F_PWM_INT_MASK   0xE000
#define	POWERSTEP2_V_CONFIG_F_PWM_DEC_19_5_KHZ   0x0000
#define	POWERSTEP2_V_CONFIG_F_PWM_DEC_31_3_KHZ   0x0C00
#define	POWERSTEP2_V_CONFIG_F_PWM_DEC_62_5_KHZ   0x1C00
#define	POWERSTEP2_V_CONFIG_F_PWM_DEC_MASK   0x1C00
#define	POWERSTEP2_V_CONFIG_VCCVAL_7_5_V   0x0000
#define	POWERSTEP2_V_CONFIG_VCCVAL_15_V   0x0200
#define	POWERSTEP2_V_CONFIG_VCCVAL_MASK   0x0200
#define	POWERSTEP2_V_CONFIG_UVLOVAL_LOW   0x0000
#define	POWERSTEP2_V_CONFIG_UVLOVAL_HIGH   0x0100
#define	POWERSTEP2_V_CONFIG_UVLOVAL_MASK   0x0100
#define	POWERSTEP2_V_CONFIG_OC_SD_DISABLE   0x0000
#define	POWERSTEP2_V_CONFIG_OC_SD_ENABLE   0x0080
#define	POWERSTEP2_V_CONFIG_OC_SD_MASK   0x0080
#define	POWERSTEP2_V_CONFIG_EN_VSCOMP_DISABLE   0x0000
#define	POWERSTEP2_V_CONFIG_EN_VSCOMP_ENABLE   0x0020
#define	POWERSTEP2_V_CONFIG_EN_VSCOMP_MASK   0x0020
#define	POWERSTEP2_V_CONFIG_SW_MODE_HARD_STOP_INT   0x0000
#define	POWERSTEP2_V_CONFIG_SW_MODE_USER_DISPOSAL   0x0010
#define	POWERSTEP2_V_CONFIG_SW_MODE_MASK   0x0010
#define	POWERSTEP2_V_CONFIG_EXT_CLK_DISABLE   0x0000
#define	POWERSTEP2_V_CONFIG_EXT_CLK_ENABLE   0x0008
#define	POWERSTEP2_V_CONFIG_EXT_CLK_MASK   0x0008
#define	POWERSTEP2_V_CONFIG_OSC_SEL_INT_16_MHZ   0x0000
#define	POWERSTEP2_V_CONFIG_OSC_SEL_MASK   0x0007
#define	POWERSTEP2_V_CONFIG_MASK   0xFFFF
#define	POWERSTEP2_C_TVAL_HOLD_7_8_MV   0x00
#define	POWERSTEP2_C_TVAL_HOLD_15_6_MV   0x01
#define	POWERSTEP2_C_TVAL_HOLD_202_8_MV   0x19
#define	POWERSTEP2_C_TVAL_HOLD_327_6_MV   0x29
#define	POWERSTEP2_C_TVAL_HOLD_1000_MV   0x7F
#define	POWERSTEP2_C_TVAL_HOLD_MASK   0x7F
#define	POWERSTEP2_C_TVAL_RUN_7_8_MV   0x00
#define	POWERSTEP2_C_TVAL_RUN_15_6_MV   0x01
#define	POWERSTEP2_C_TVAL_RUN_202_8_MV   0x19
#define	POWERSTEP2_C_TVAL_RUN_327_6_MV   0x29
#define	POWERSTEP2_C_TVAL_RUN_1000_MV   0x7F
#define	POWERSTEP2_C_TVAL_RUN_MASK   0x7F
#define	POWERSTEP2_C_TVAL_ACC_7_8_MV   0x00
#define	POWERSTEP2_C_TVAL_ACC_15_6_MV   0x01
#define	POWERSTEP2_C_TVAL_ACC_202_8_MV   0x19
#define	POWERSTEP2_C_TVAL_ACC_327_6_MV   0x29
#define	POWERSTEP2_C_TVAL_ACC_1000_MV   0x7F
#define	POWERSTEP2_C_TVAL_ACC_MASK   0x7F
#define	POWERSTEP2_C_TVAL_DEC_7_8_MV   0x00
#define	POWERSTEP2_C_TVAL_DEC_15_6_MV   0x01
#define	POWERSTEP2_C_TVAL_DEC_202_8_MV   0x19
#define	POWERSTEP2_C_TVAL_DEC_327_6_MV   0x29
#define	POWERSTEP2_C_TVAL_DEC_1000_MV   0x7F
#define	POWERSTEP2_C_TVAL_DEC_MASK   0x7F
#define	POWERSTEP2_C_T_FAST_TOFF_FAST_2_US   0x00
#define	POWERSTEP2_C_T_FAST_TOFF_FAST_4_US   0x10
#define	POWERSTEP2_C_T_FAST_TOFF_FAST_10_US   0x40
#define	POWERSTEP2_C_T_FAST_TOFF_FAST_32_US   0xF0
#define	POWERSTEP2_C_T_FAST_TOFF_FAST_MASK   0xF0
#define	POWERSTEP2_C_T_FAST_FAST_STEP_2_US   0x00
#define	POWERSTEP2_C_T_FAST_FAST_STEP_4_US   0x01
#define	POWERSTEP2_C_T_FAST_FAST_STEP_10_US   0x04
#define	POWERSTEP2_C_T_FAST_FAST_STEP_16_US   0x07
#define	POWERSTEP2_C_T_FAST_FAST_STEP_32_US   0x0F
#define	POWERSTEP2_C_T_FAST_FAST_STEP_MASK   0x0F
#define	POWERSTEP2_C_T_FAST_MASK   0xFF
#define	POWERSTEP2_C_TON_MIN_0_5_US   0x00
#define	POWERSTEP2_C_TON_MIN_1_US   0x01
#define	POWERSTEP2_C_TON_MIN_2_5_US   0x04
#define	POWERSTEP2_C_TON_MIN_64_US   0x7F
#define	POWERSTEP2_C_TON_MIN_MASK   0x7F
#define	POWERSTEP2_C_TOFF_MIN_0_5_US   0x00
#define	POWERSTEP2_C_TOFF_MIN_1_US   0x01
#define	POWERSTEP2_C_TOFF_MIN_2_5_US   0x04
#define	POWERSTEP2_C_TOFF_MIN_21_US   0x29
#define	POWERSTEP2_C_TOFF_MIN_64_US   0x7F
#define	POWERSTEP2_C_TOFF_MIN_MASK   0x7F
#define	POWERSTEP2_C_CONFIG_PRED_EN_DISABLE   0x0000
#define	POWERSTEP2_C_CONFIG_PRED_EN_ENABLE   0x8000
#define	POWERSTEP2_C_CONFIG_PRED_EN_MASK   0x8000
#define	POWERSTEP2_C_CONFIG_TSW_4_US   0x0400
#define	POWERSTEP2_C_CONFIG_TSW_8_US   0x0800
#define	POWERSTEP2_C_CONFIG_TSW_48_US   0x3000
#define	POWERSTEP2_C_CONFIG_TSW_124_US   0x7C00
#define	POWERSTEP2_C_CONFIG_TSW_MASK   0x7C00
#define	POWERSTEP2_C_CONFIG_VCCVAL_7_5_V   0x0000
#define	POWERSTEP2_C_CONFIG_VCCVAL_15_V   0x0200
#define	POWERSTEP2_C_CONFIG_VCCVAL_MASK   0x0200
#define	POWERSTEP2_C_CONFIG_UVLOVAL_LOW   0x0000
#define	POWERSTEP2_C_CONFIG_UVLOVAL_HIGH   0x0100
#define	POWERSTEP2_C_CONFIG_UVLOVAL_MASK   0x0100
#define	POWERSTEP2_C_CONFIG_OC_SD_DISABLE   0x0000
#define	POWERSTEP2_C_CONFIG_OC_SD_ENABLE   0x0080
#define	POWERSTEP2_C_CONFIG_OC_SD_MASK   0x0080
#define	POWERSTEP2_C_CONFIG_EN_TQREG_DISABLE   0x0000
#define	POWERSTEP2_C_CONFIG_EN_TQREG_ENABLE   0x0020
#define	POWERSTEP2_C_CONFIG_EN_TQREG_MASK   0x0020
#define	POWERSTEP2_C_CONFIG_SW_MODE_HARD_STOP_INT   0x0000
#define	POWERSTEP2_C_CONFIG_SW_MODE_USER_DISPOSAL   0x0010
#define	POWERSTEP2_C_CONFIG_SW_MODE_MASK   0x0010
#define	POWERSTEP2_C_CONFIG_EXT_CLK_DISABLE   0x0000
#define	POWERSTEP2_C_CONFIG_EXT_CLK_ENABLE   0x0008
#define	POWERSTEP2_C_CONFIG_EXT_CLK_MASK   0x0008
#define	POWERSTEP2_C_CONFIG_OSC_SEL_INT_16_MHZ   0x0000
#define	POWERSTEP2_C_CONFIG_OSC_SEL_MASK   0x0007
#define	POWERSTEP2_C_CONFIG_MASK   0xFFFF
#define	POWERSTEP2_GEN_ABS_POS_DEF   ( POWERSTEP2_GEN_ABS_POS_HOME )
	Power Step 2 parameter register default settings.
#define	POWERSTEP2_GEN_EL_POS_DEF
#define	POWERSTEP2_GEN_MARK_DEF   ( POWERSTEP2_GEN_MARK_ZERO )
#define	POWERSTEP2_GEN_ACC_DEF   ( POWERSTEP2_GEN_ACC_101_85_STEP_S2 )
#define	POWERSTEP2_GEN_DEC_DEF   ( POWERSTEP2_GEN_DEC_101_85_STEP_S2 )
#define	POWERSTEP2_GEN_MAX_SPEED_DEF   ( POWERSTEP2_GEN_MAX_SPEED_305_STEP_S )
#define	POWERSTEP2_GEN_MIN_SPEED_DEF
#define	POWERSTEP2_GEN_OCD_TH_DEF   ( POWERSTEP2_GEN_OCD_TH_531_25_MV )
#define	POWERSTEP2_GEN_FS_SPD_DEF
#define	POWERSTEP2_GEN_STEP_MODE_DEF
#define	POWERSTEP2_GEN_ALARM_EN_DEF
#define	POWERSTEP2_GEN_GATECFG1_DEF
#define	POWERSTEP2_GEN_GATECFG2_DEF
#define	POWERSTEP2_V_CONFIG_DEF
#define	POWERSTEP2_V_KVAL_HOLD_DEF   ( POWERSTEP2_V_KVAL_HOLD_0_168_VS )
#define	POWERSTEP2_V_KVAL_RUN_DEF   ( POWERSTEP2_V_KVAL_RUN_0_168_VS )
#define	POWERSTEP2_V_KVAL_ACC_DEF   ( POWERSTEP2_V_KVAL_ACC_0_168_VS )
#define	POWERSTEP2_V_KVAL_DEC_DEF   ( POWERSTEP2_V_KVAL_DEC_0_168_VS )
#define	POWERSTEP2_V_INT_SPEED_DEF   ( POWERSTEP2_V_INT_SPEED_61_5668_STEP_S )
#define	POWERSTEP2_V_ST_SLP_DEF   ( POWERSTEP2_V_ST_SLP_0_000135 )
#define	POWERSTEP2_V_FN_SLP_ACC_DEF   ( POWERSTEP2_V_FN_SLP_ACC_0_00063 )
#define	POWERSTEP2_V_FN_SLP_DEC_DEF   ( POWERSTEP2_V_FN_SLP_DEC_0_00063 )
#define	POWERSTEP2_V_K_THERM_DEF   ( POWERSTEP2_V_K_THERM_1 )
#define	POWERSTEP2_V_STALL_TH_DEF   ( POWERSTEP2_V_STALL_TH_531_25_MV )
#define	POWERSTEP2_C_CONFIG_DEF
#define	POWERSTEP2_C_TVAL_HOLD_DEF   ( POWERSTEP2_C_TVAL_HOLD_327_6_MV )
#define	POWERSTEP2_C_TVAL_RUN_DEF   ( POWERSTEP2_C_TVAL_RUN_327_6_MV )
#define	POWERSTEP2_C_TVAL_ACC_DEF   ( POWERSTEP2_C_TVAL_ACC_327_6_MV )
#define	POWERSTEP2_C_TVAL_DEC_DEF   ( POWERSTEP2_C_TVAL_DEC_327_6_MV )
#define	POWERSTEP2_C_T_FAST_DEF
#define	POWERSTEP2_C_TON_MIN_DEF   ( POWERSTEP2_C_TON_MIN_2_5_US )
#define	POWERSTEP2_C_TOFF_MIN_DEF   ( POWERSTEP2_C_TOFF_MIN_21_US )
#define	POWERSTEP2_CONTROL_MODE_VOLTAGE   0
	Power Step 2 control mode setting.
#define	POWERSTEP2_CONTROL_MODE_CURRENT   1
#define	POWERSTEP2_STEP_MODE_FULL_STEP   0
	Power Step 2 step mode setting.
#define	POWERSTEP2_STEP_MODE_HALF_STEP   1
#define	POWERSTEP2_STEP_MODE_QUARTER_STEP   2
#define	POWERSTEP2_STEP_MODE_1_OVER_8   3
#define	POWERSTEP2_STEP_MODE_1_OVER_16   4
#define	POWERSTEP2_STEP_MODE_1_OVER_32   5
#define	POWERSTEP2_STEP_MODE_1_OVER_64   6
#define	POWERSTEP2_STEP_MODE_1_OVER_128   7
#define	POWERSTEP2_ACCELERATION_STEP   14.55f
	Power Step 2 acceleration and deceleration settings.
#define	POWERSTEP2_ACCELERATION_MIN   14.55f
#define	POWERSTEP2_ACCELERATION_MAX   59575.541f
#define	POWERSTEP2_DECELERATION_STEP   14.55f
#define	POWERSTEP2_DECELERATION_MIN   14.55f
#define	POWERSTEP2_DECELERATION_MAX   59575.541f
#define	POWERSTEP2_MIN_SPEED_STEP   0.238f
	Power Step 2 speed min and max settings.
#define	POWERSTEP2_MIN_SPEED_MIN   0.0f
#define	POWERSTEP2_MIN_SPEED_MAX   976.3f
#define	POWERSTEP2_MAX_SPEED_STEP   15.25f
#define	POWERSTEP2_MAX_SPEED_MIN   15.25f
#define	POWERSTEP2_MAX_SPEED_MAX   15610.0f
#define	POWERSTEP2_DIR_CW   1
	Power Step 2 direction setting.
#define	POWERSTEP2_DIR_CCW   0
#define	POWERSTEP2_PIN_LOW_LEVEL   0
	Power Step 2 pin logic level setting.
#define	POWERSTEP2_PIN_HIGH_LEVEL   1
#define	POWERSTEP2_SPEED_VERY_SLOW   0
	Power Step 2 driving speed in step clock mode settings.
#define	POWERSTEP2_SPEED_SLOW   1
#define	POWERSTEP2_SPEED_MEDIUM   2
#define	POWERSTEP2_SPEED_FAST   3
#define	POWERSTEP2_SPEED_VERY_FAST   4
#define	POWERSTEP2_ROUND_TO_INT   0.5f
	Power Step 2 round to upper int settings.
#define	POWERSTEP2_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.
#define	POWERSTEP2_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of Power Step 2 Click driver.

Macro Definition Documentation

POWERSTEP2_ACCELERATION_MAX

#define POWERSTEP2_ACCELERATION_MAX   59575.541f

POWERSTEP2_ACCELERATION_MIN

#define POWERSTEP2_ACCELERATION_MIN   14.55f

POWERSTEP2_ACCELERATION_STEP

#define POWERSTEP2_ACCELERATION_STEP   14.55f

Power Step 2 acceleration and deceleration settings.

Specified acceleration and deceleration settings in step/s2 of Power Step 2 Click driver.

POWERSTEP2_C_CONFIG_DEF

#define POWERSTEP2_C_CONFIG_DEF

Value:

                                                          ( POWERSTEP2_C_CONFIG_PRED_EN_DISABLE | \
                                                          POWERSTEP2_C_CONFIG_TSW_48_US | \
                                                          POWERSTEP2_C_CONFIG_VCCVAL_15_V | \
                                                          POWERSTEP2_C_CONFIG_UVLOVAL_LOW | \
                                                          POWERSTEP2_C_CONFIG_OC_SD_ENABLE | \
                                                          POWERSTEP2_C_CONFIG_EN_TQREG_DISABLE | \
                                                          POWERSTEP2_C_CONFIG_SW_MODE_HARD_STOP_INT | \
                                                          POWERSTEP2_C_CONFIG_EXT_CLK_DISABLE | \
                                                          POWERSTEP2_C_CONFIG_OSC_SEL_INT_16_MHZ )

POWERSTEP2_C_CONFIG_EN_TQREG_DISABLE

#define POWERSTEP2_C_CONFIG_EN_TQREG_DISABLE   0x0000

POWERSTEP2_C_CONFIG_EN_TQREG_ENABLE

#define POWERSTEP2_C_CONFIG_EN_TQREG_ENABLE   0x0020

POWERSTEP2_C_CONFIG_EN_TQREG_MASK

#define POWERSTEP2_C_CONFIG_EN_TQREG_MASK   0x0020

POWERSTEP2_C_CONFIG_EXT_CLK_DISABLE

#define POWERSTEP2_C_CONFIG_EXT_CLK_DISABLE   0x0000

POWERSTEP2_C_CONFIG_EXT_CLK_ENABLE

#define POWERSTEP2_C_CONFIG_EXT_CLK_ENABLE   0x0008

POWERSTEP2_C_CONFIG_EXT_CLK_MASK

#define POWERSTEP2_C_CONFIG_EXT_CLK_MASK   0x0008

POWERSTEP2_C_CONFIG_MASK

#define POWERSTEP2_C_CONFIG_MASK   0xFFFF

POWERSTEP2_C_CONFIG_OC_SD_DISABLE

#define POWERSTEP2_C_CONFIG_OC_SD_DISABLE   0x0000

POWERSTEP2_C_CONFIG_OC_SD_ENABLE

#define POWERSTEP2_C_CONFIG_OC_SD_ENABLE   0x0080

POWERSTEP2_C_CONFIG_OC_SD_MASK

#define POWERSTEP2_C_CONFIG_OC_SD_MASK   0x0080

POWERSTEP2_C_CONFIG_OSC_SEL_INT_16_MHZ

#define POWERSTEP2_C_CONFIG_OSC_SEL_INT_16_MHZ   0x0000

POWERSTEP2_C_CONFIG_OSC_SEL_MASK

#define POWERSTEP2_C_CONFIG_OSC_SEL_MASK   0x0007

POWERSTEP2_C_CONFIG_PRED_EN_DISABLE

#define POWERSTEP2_C_CONFIG_PRED_EN_DISABLE   0x0000

POWERSTEP2_C_CONFIG_PRED_EN_ENABLE

#define POWERSTEP2_C_CONFIG_PRED_EN_ENABLE   0x8000

POWERSTEP2_C_CONFIG_PRED_EN_MASK

#define POWERSTEP2_C_CONFIG_PRED_EN_MASK   0x8000

POWERSTEP2_C_CONFIG_SW_MODE_HARD_STOP_INT

#define POWERSTEP2_C_CONFIG_SW_MODE_HARD_STOP_INT   0x0000

POWERSTEP2_C_CONFIG_SW_MODE_MASK

#define POWERSTEP2_C_CONFIG_SW_MODE_MASK   0x0010

POWERSTEP2_C_CONFIG_SW_MODE_USER_DISPOSAL

#define POWERSTEP2_C_CONFIG_SW_MODE_USER_DISPOSAL   0x0010

POWERSTEP2_C_CONFIG_TSW_124_US

#define POWERSTEP2_C_CONFIG_TSW_124_US   0x7C00

POWERSTEP2_C_CONFIG_TSW_48_US

#define POWERSTEP2_C_CONFIG_TSW_48_US   0x3000

POWERSTEP2_C_CONFIG_TSW_4_US

#define POWERSTEP2_C_CONFIG_TSW_4_US   0x0400

POWERSTEP2_C_CONFIG_TSW_8_US

#define POWERSTEP2_C_CONFIG_TSW_8_US   0x0800

POWERSTEP2_C_CONFIG_TSW_MASK

#define POWERSTEP2_C_CONFIG_TSW_MASK   0x7C00

POWERSTEP2_C_CONFIG_UVLOVAL_HIGH

#define POWERSTEP2_C_CONFIG_UVLOVAL_HIGH   0x0100

POWERSTEP2_C_CONFIG_UVLOVAL_LOW

#define POWERSTEP2_C_CONFIG_UVLOVAL_LOW   0x0000

POWERSTEP2_C_CONFIG_UVLOVAL_MASK

#define POWERSTEP2_C_CONFIG_UVLOVAL_MASK   0x0100

POWERSTEP2_C_CONFIG_VCCVAL_15_V

#define POWERSTEP2_C_CONFIG_VCCVAL_15_V   0x0200

POWERSTEP2_C_CONFIG_VCCVAL_7_5_V

#define POWERSTEP2_C_CONFIG_VCCVAL_7_5_V   0x0000

POWERSTEP2_C_CONFIG_VCCVAL_MASK

#define POWERSTEP2_C_CONFIG_VCCVAL_MASK   0x0200

POWERSTEP2_C_T_FAST_DEF

#define POWERSTEP2_C_T_FAST_DEF

Value:

                                                          ( POWERSTEP2_C_T_FAST_TOFF_FAST_10_US | \
                                                          POWERSTEP2_C_T_FAST_FAST_STEP_16_US )

POWERSTEP2_C_T_FAST_FAST_STEP_10_US

#define POWERSTEP2_C_T_FAST_FAST_STEP_10_US   0x04

POWERSTEP2_C_T_FAST_FAST_STEP_16_US

#define POWERSTEP2_C_T_FAST_FAST_STEP_16_US   0x07

POWERSTEP2_C_T_FAST_FAST_STEP_2_US

#define POWERSTEP2_C_T_FAST_FAST_STEP_2_US   0x00

POWERSTEP2_C_T_FAST_FAST_STEP_32_US

#define POWERSTEP2_C_T_FAST_FAST_STEP_32_US   0x0F

POWERSTEP2_C_T_FAST_FAST_STEP_4_US

#define POWERSTEP2_C_T_FAST_FAST_STEP_4_US   0x01

POWERSTEP2_C_T_FAST_FAST_STEP_MASK

#define POWERSTEP2_C_T_FAST_FAST_STEP_MASK   0x0F

POWERSTEP2_C_T_FAST_MASK

#define POWERSTEP2_C_T_FAST_MASK   0xFF

POWERSTEP2_C_T_FAST_TOFF_FAST_10_US

#define POWERSTEP2_C_T_FAST_TOFF_FAST_10_US   0x40

POWERSTEP2_C_T_FAST_TOFF_FAST_2_US

#define POWERSTEP2_C_T_FAST_TOFF_FAST_2_US   0x00

POWERSTEP2_C_T_FAST_TOFF_FAST_32_US

#define POWERSTEP2_C_T_FAST_TOFF_FAST_32_US   0xF0

POWERSTEP2_C_T_FAST_TOFF_FAST_4_US

#define POWERSTEP2_C_T_FAST_TOFF_FAST_4_US   0x10

POWERSTEP2_C_T_FAST_TOFF_FAST_MASK

#define POWERSTEP2_C_T_FAST_TOFF_FAST_MASK   0xF0

POWERSTEP2_C_TOFF_MIN_0_5_US

#define POWERSTEP2_C_TOFF_MIN_0_5_US   0x00

POWERSTEP2_C_TOFF_MIN_1_US

#define POWERSTEP2_C_TOFF_MIN_1_US   0x01

POWERSTEP2_C_TOFF_MIN_21_US

#define POWERSTEP2_C_TOFF_MIN_21_US   0x29

POWERSTEP2_C_TOFF_MIN_2_5_US

#define POWERSTEP2_C_TOFF_MIN_2_5_US   0x04

POWERSTEP2_C_TOFF_MIN_64_US

#define POWERSTEP2_C_TOFF_MIN_64_US   0x7F

POWERSTEP2_C_TOFF_MIN_DEF

#define POWERSTEP2_C_TOFF_MIN_DEF   ( POWERSTEP2_C_TOFF_MIN_21_US )

POWERSTEP2_C_TOFF_MIN_MASK

#define POWERSTEP2_C_TOFF_MIN_MASK   0x7F

POWERSTEP2_C_TON_MIN_0_5_US

#define POWERSTEP2_C_TON_MIN_0_5_US   0x00

POWERSTEP2_C_TON_MIN_1_US

#define POWERSTEP2_C_TON_MIN_1_US   0x01

POWERSTEP2_C_TON_MIN_2_5_US

#define POWERSTEP2_C_TON_MIN_2_5_US   0x04

POWERSTEP2_C_TON_MIN_64_US

#define POWERSTEP2_C_TON_MIN_64_US   0x7F

POWERSTEP2_C_TON_MIN_DEF

#define POWERSTEP2_C_TON_MIN_DEF   ( POWERSTEP2_C_TON_MIN_2_5_US )

POWERSTEP2_C_TON_MIN_MASK

#define POWERSTEP2_C_TON_MIN_MASK   0x7F

POWERSTEP2_C_TVAL_ACC_1000_MV

#define POWERSTEP2_C_TVAL_ACC_1000_MV   0x7F

POWERSTEP2_C_TVAL_ACC_15_6_MV

#define POWERSTEP2_C_TVAL_ACC_15_6_MV   0x01

POWERSTEP2_C_TVAL_ACC_202_8_MV

#define POWERSTEP2_C_TVAL_ACC_202_8_MV   0x19

POWERSTEP2_C_TVAL_ACC_327_6_MV

#define POWERSTEP2_C_TVAL_ACC_327_6_MV   0x29

POWERSTEP2_C_TVAL_ACC_7_8_MV

#define POWERSTEP2_C_TVAL_ACC_7_8_MV   0x00

POWERSTEP2_C_TVAL_ACC_DEF

#define POWERSTEP2_C_TVAL_ACC_DEF   ( POWERSTEP2_C_TVAL_ACC_327_6_MV )

POWERSTEP2_C_TVAL_ACC_MASK

#define POWERSTEP2_C_TVAL_ACC_MASK   0x7F

POWERSTEP2_C_TVAL_DEC_1000_MV

#define POWERSTEP2_C_TVAL_DEC_1000_MV   0x7F

POWERSTEP2_C_TVAL_DEC_15_6_MV

#define POWERSTEP2_C_TVAL_DEC_15_6_MV   0x01

POWERSTEP2_C_TVAL_DEC_202_8_MV

#define POWERSTEP2_C_TVAL_DEC_202_8_MV   0x19

POWERSTEP2_C_TVAL_DEC_327_6_MV

#define POWERSTEP2_C_TVAL_DEC_327_6_MV   0x29

POWERSTEP2_C_TVAL_DEC_7_8_MV

#define POWERSTEP2_C_TVAL_DEC_7_8_MV   0x00

POWERSTEP2_C_TVAL_DEC_DEF

#define POWERSTEP2_C_TVAL_DEC_DEF   ( POWERSTEP2_C_TVAL_DEC_327_6_MV )

POWERSTEP2_C_TVAL_DEC_MASK

#define POWERSTEP2_C_TVAL_DEC_MASK   0x7F

POWERSTEP2_C_TVAL_HOLD_1000_MV

#define POWERSTEP2_C_TVAL_HOLD_1000_MV   0x7F

POWERSTEP2_C_TVAL_HOLD_15_6_MV

#define POWERSTEP2_C_TVAL_HOLD_15_6_MV   0x01

POWERSTEP2_C_TVAL_HOLD_202_8_MV

#define POWERSTEP2_C_TVAL_HOLD_202_8_MV   0x19

POWERSTEP2_C_TVAL_HOLD_327_6_MV

#define POWERSTEP2_C_TVAL_HOLD_327_6_MV   0x29

POWERSTEP2_C_TVAL_HOLD_7_8_MV

#define POWERSTEP2_C_TVAL_HOLD_7_8_MV   0x00

POWERSTEP2_C_TVAL_HOLD_DEF

#define POWERSTEP2_C_TVAL_HOLD_DEF   ( POWERSTEP2_C_TVAL_HOLD_327_6_MV )

POWERSTEP2_C_TVAL_HOLD_MASK

#define POWERSTEP2_C_TVAL_HOLD_MASK   0x7F

POWERSTEP2_C_TVAL_RUN_1000_MV

#define POWERSTEP2_C_TVAL_RUN_1000_MV   0x7F

POWERSTEP2_C_TVAL_RUN_15_6_MV

#define POWERSTEP2_C_TVAL_RUN_15_6_MV   0x01

POWERSTEP2_C_TVAL_RUN_202_8_MV

#define POWERSTEP2_C_TVAL_RUN_202_8_MV   0x19

POWERSTEP2_C_TVAL_RUN_327_6_MV

#define POWERSTEP2_C_TVAL_RUN_327_6_MV   0x29

POWERSTEP2_C_TVAL_RUN_7_8_MV

#define POWERSTEP2_C_TVAL_RUN_7_8_MV   0x00

POWERSTEP2_C_TVAL_RUN_DEF

#define POWERSTEP2_C_TVAL_RUN_DEF   ( POWERSTEP2_C_TVAL_RUN_327_6_MV )

POWERSTEP2_C_TVAL_RUN_MASK

#define POWERSTEP2_C_TVAL_RUN_MASK   0x7F

POWERSTEP2_CONTROL_MODE_CURRENT

#define POWERSTEP2_CONTROL_MODE_CURRENT   1

POWERSTEP2_CONTROL_MODE_VOLTAGE

#define POWERSTEP2_CONTROL_MODE_VOLTAGE   0

Power Step 2 control mode setting.

Specified setting for control mode of Power Step 2 Click driver.

POWERSTEP2_DECELERATION_MAX

#define POWERSTEP2_DECELERATION_MAX   59575.541f

POWERSTEP2_DECELERATION_MIN

#define POWERSTEP2_DECELERATION_MIN   14.55f

POWERSTEP2_DECELERATION_STEP

#define POWERSTEP2_DECELERATION_STEP   14.55f

POWERSTEP2_DIR_CCW

#define POWERSTEP2_DIR_CCW   0

POWERSTEP2_DIR_CW

#define POWERSTEP2_DIR_CW   1

Power Step 2 direction setting.

Specified setting for direction of Power Step 2 Click driver.

POWERSTEP2_GEN_ABS_POS_DEF

#define POWERSTEP2_GEN_ABS_POS_DEF   ( POWERSTEP2_GEN_ABS_POS_HOME )

Power Step 2 parameter register default settings.

Specified parameter register default settings of Power Step 2 Click driver.

POWERSTEP2_GEN_ABS_POS_HOME

#define POWERSTEP2_GEN_ABS_POS_HOME   0x000000ul

Power Step 2 parameter register settings.

Specified parameter register settings of Power Step 2 Click driver.

POWERSTEP2_GEN_ABS_POS_MASK

#define POWERSTEP2_GEN_ABS_POS_MASK   0x3FFFFFul

POWERSTEP2_GEN_ACC_1004_STEP_S2 [1/2]

#define POWERSTEP2_GEN_ACC_1004_STEP_S2   0x0045

POWERSTEP2_GEN_ACC_1004_STEP_S2 [2/2]

#define POWERSTEP2_GEN_ACC_1004_STEP_S2   0x0045

POWERSTEP2_GEN_ACC_101_85_STEP_S2

#define POWERSTEP2_GEN_ACC_101_85_STEP_S2   0x0007

POWERSTEP2_GEN_ACC_14_55_STEP_S2

#define POWERSTEP2_GEN_ACC_14_55_STEP_S2   0x0001

POWERSTEP2_GEN_ACC_2008_STEP_S2

#define POWERSTEP2_GEN_ACC_2008_STEP_S2   0x008A

POWERSTEP2_GEN_ACC_29_1_STEP_S2

#define POWERSTEP2_GEN_ACC_29_1_STEP_S2   0x0002

POWERSTEP2_GEN_ACC_59575_541_STEP_S2

#define POWERSTEP2_GEN_ACC_59575_541_STEP_S2   0x0FFF

POWERSTEP2_GEN_ACC_DEF

#define POWERSTEP2_GEN_ACC_DEF   ( POWERSTEP2_GEN_ACC_101_85_STEP_S2 )

POWERSTEP2_GEN_ACC_MASK

#define POWERSTEP2_GEN_ACC_MASK   0x0FFF

POWERSTEP2_GEN_ADC_OUT_MASK

#define POWERSTEP2_GEN_ADC_OUT_MASK   0x1F

POWERSTEP2_GEN_ALARM_EN_ADC_UVLO_MASK

#define POWERSTEP2_GEN_ALARM_EN_ADC_UVLO_MASK   0x10

POWERSTEP2_GEN_ALARM_EN_CMD_ERROR_MASK

#define POWERSTEP2_GEN_ALARM_EN_CMD_ERROR_MASK   0x80

POWERSTEP2_GEN_ALARM_EN_DEF

#define POWERSTEP2_GEN_ALARM_EN_DEF

Value:

                                                          ( POWERSTEP2_GEN_ALARM_EN_CMD_ERROR_MASK | \
                                                          POWERSTEP2_GEN_ALARM_EN_SW_ON_MASK | \
                                                          POWERSTEP2_GEN_ALARM_EN_STALL_DET_MASK | \
                                                          POWERSTEP2_GEN_ALARM_EN_UVLO_MASK | \
                                                          POWERSTEP2_GEN_ALARM_EN_THERMAL_WARN_MASK | \
                                                          POWERSTEP2_GEN_ALARM_EN_THERMAL_SD_MASK | \
                                                          POWERSTEP2_GEN_ALARM_EN_OVERCURRENT_MASK )

POWERSTEP2_GEN_ALARM_EN_MASK

#define POWERSTEP2_GEN_ALARM_EN_MASK   0xFF

POWERSTEP2_GEN_ALARM_EN_OVERCURRENT_MASK

#define POWERSTEP2_GEN_ALARM_EN_OVERCURRENT_MASK   0x01

POWERSTEP2_GEN_ALARM_EN_STALL_DET_MASK

#define POWERSTEP2_GEN_ALARM_EN_STALL_DET_MASK   0x20

POWERSTEP2_GEN_ALARM_EN_SW_ON_MASK

#define POWERSTEP2_GEN_ALARM_EN_SW_ON_MASK   0x40

POWERSTEP2_GEN_ALARM_EN_THERMAL_SD_MASK

#define POWERSTEP2_GEN_ALARM_EN_THERMAL_SD_MASK   0x02

POWERSTEP2_GEN_ALARM_EN_THERMAL_WARN_MASK

#define POWERSTEP2_GEN_ALARM_EN_THERMAL_WARN_MASK   0x04

POWERSTEP2_GEN_ALARM_EN_UVLO_MASK

#define POWERSTEP2_GEN_ALARM_EN_UVLO_MASK   0x08

POWERSTEP2_GEN_DEC_1004_STEP_S2

#define POWERSTEP2_GEN_DEC_1004_STEP_S2   0x0045

POWERSTEP2_GEN_DEC_101_85_STEP_S2

#define POWERSTEP2_GEN_DEC_101_85_STEP_S2   0x0007

POWERSTEP2_GEN_DEC_14_55_STEP_S2

#define POWERSTEP2_GEN_DEC_14_55_STEP_S2   0x0001

POWERSTEP2_GEN_DEC_2008_STEP_S2

#define POWERSTEP2_GEN_DEC_2008_STEP_S2   0x008A

POWERSTEP2_GEN_DEC_29_1_STEP_S2

#define POWERSTEP2_GEN_DEC_29_1_STEP_S2   0x0002

POWERSTEP2_GEN_DEC_59575_541_STEP_S2

#define POWERSTEP2_GEN_DEC_59575_541_STEP_S2   0x0FFF

POWERSTEP2_GEN_DEC_DEF

#define POWERSTEP2_GEN_DEC_DEF   ( POWERSTEP2_GEN_DEC_101_85_STEP_S2 )

POWERSTEP2_GEN_DEC_MASK

#define POWERSTEP2_GEN_DEC_MASK   0x0FFF

POWERSTEP2_GEN_EL_POS_DEF

#define POWERSTEP2_GEN_EL_POS_DEF

Value:

                                                          ( POWERSTEP2_GEN_EL_POS_STEP_ZERO | \
                                                          POWERSTEP2_GEN_EL_POS_MICROSTEP_ZERO )

POWERSTEP2_GEN_EL_POS_MASK

#define POWERSTEP2_GEN_EL_POS_MASK   0x01FF

POWERSTEP2_GEN_EL_POS_MICROSTEP_MASK

#define POWERSTEP2_GEN_EL_POS_MICROSTEP_MASK   0x007F

POWERSTEP2_GEN_EL_POS_MICROSTEP_ZERO

#define POWERSTEP2_GEN_EL_POS_MICROSTEP_ZERO   0x0000

POWERSTEP2_GEN_EL_POS_STEP_MASK

#define POWERSTEP2_GEN_EL_POS_STEP_MASK   0x0180

POWERSTEP2_GEN_EL_POS_STEP_ZERO

#define POWERSTEP2_GEN_EL_POS_STEP_ZERO   0x0000

POWERSTEP2_GEN_FS_SPD_BOOST_MODE_DISABLE

#define POWERSTEP2_GEN_FS_SPD_BOOST_MODE_DISABLE   0x0000

POWERSTEP2_GEN_FS_SPD_BOOST_MODE_ENABLE

#define POWERSTEP2_GEN_FS_SPD_BOOST_MODE_ENABLE   0x0400

POWERSTEP2_GEN_FS_SPD_BOOST_MODE_MASK

#define POWERSTEP2_GEN_FS_SPD_BOOST_MODE_MASK   0x0400

POWERSTEP2_GEN_FS_SPD_DEF

#define POWERSTEP2_GEN_FS_SPD_DEF

Value:

                                                          ( POWERSTEP2_GEN_FS_SPD_BOOST_MODE_DISABLE | \
                                                          POWERSTEP2_GEN_FS_SPD_FS_SPD_15617_STEP_S )

POWERSTEP2_GEN_FS_SPD_FS_SPD_15617_STEP_S

#define POWERSTEP2_GEN_FS_SPD_FS_SPD_15617_STEP_S   0x03FF

POWERSTEP2_GEN_FS_SPD_FS_SPD_22_88_STEP_S

#define POWERSTEP2_GEN_FS_SPD_FS_SPD_22_88_STEP_S   0x0001

POWERSTEP2_GEN_FS_SPD_FS_SPD_38_13_STEP_S

#define POWERSTEP2_GEN_FS_SPD_FS_SPD_38_13_STEP_S   0x0002

POWERSTEP2_GEN_FS_SPD_FS_SPD_7_63_STEP_S

#define POWERSTEP2_GEN_FS_SPD_FS_SPD_7_63_STEP_S   0x0000

POWERSTEP2_GEN_FS_SPD_FS_SPD_MASK

#define POWERSTEP2_GEN_FS_SPD_FS_SPD_MASK   0x03FF

POWERSTEP2_GEN_FS_SPD_MASK

#define POWERSTEP2_GEN_FS_SPD_MASK   0x07FF

POWERSTEP2_GEN_GATECFG1_DEF

#define POWERSTEP2_GEN_GATECFG1_DEF

Value:

                                                          ( POWERSTEP2_GEN_GATECFG1_WD_EN_DISABLE | \
                                                          POWERSTEP2_GEN_GATECFG1_TBOOST_0_NS | \
                                                          POWERSTEP2_GEN_GATECFG1_IGATE_64_MA | \
                                                          POWERSTEP2_GEN_GATECFG1_TCC_500_NS )

POWERSTEP2_GEN_GATECFG1_IGATE_16_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_16_MA   0x0060

POWERSTEP2_GEN_GATECFG1_IGATE_24_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_24_MA   0x0080

POWERSTEP2_GEN_GATECFG1_IGATE_32_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_32_MA   0x00A0

POWERSTEP2_GEN_GATECFG1_IGATE_4_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_4_MA   0x0020

POWERSTEP2_GEN_GATECFG1_IGATE_64_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_64_MA   0x00C0

POWERSTEP2_GEN_GATECFG1_IGATE_8_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_8_MA   0x0040

POWERSTEP2_GEN_GATECFG1_IGATE_96_MA

#define POWERSTEP2_GEN_GATECFG1_IGATE_96_MA   0x00E0

POWERSTEP2_GEN_GATECFG1_IGATE_MASK

#define POWERSTEP2_GEN_GATECFG1_IGATE_MASK   0x00E0

POWERSTEP2_GEN_GATECFG1_MASK

#define POWERSTEP2_GEN_GATECFG1_MASK   0x0FFF

POWERSTEP2_GEN_GATECFG1_TBOOST_0_NS

#define POWERSTEP2_GEN_GATECFG1_TBOOST_0_NS   0x0000

POWERSTEP2_GEN_GATECFG1_TBOOST_1000_NS

#define POWERSTEP2_GEN_GATECFG1_TBOOST_1000_NS   0x0700

POWERSTEP2_GEN_GATECFG1_TBOOST_62_5_NS

#define POWERSTEP2_GEN_GATECFG1_TBOOST_62_5_NS   0x0100

POWERSTEP2_GEN_GATECFG1_TBOOST_MASK

#define POWERSTEP2_GEN_GATECFG1_TBOOST_MASK   0x0700

POWERSTEP2_GEN_GATECFG1_TCC_125_NS

#define POWERSTEP2_GEN_GATECFG1_TCC_125_NS   0x0000

POWERSTEP2_GEN_GATECFG1_TCC_250_NS

#define POWERSTEP2_GEN_GATECFG1_TCC_250_NS   0x0001

POWERSTEP2_GEN_GATECFG1_TCC_3750_NS

#define POWERSTEP2_GEN_GATECFG1_TCC_3750_NS   0x001D

POWERSTEP2_GEN_GATECFG1_TCC_375_NS

#define POWERSTEP2_GEN_GATECFG1_TCC_375_NS   0x0002

POWERSTEP2_GEN_GATECFG1_TCC_500_NS

#define POWERSTEP2_GEN_GATECFG1_TCC_500_NS   0x0003

POWERSTEP2_GEN_GATECFG1_TCC_MASK

#define POWERSTEP2_GEN_GATECFG1_TCC_MASK   0x001F

POWERSTEP2_GEN_GATECFG1_WD_EN_DISABLE

#define POWERSTEP2_GEN_GATECFG1_WD_EN_DISABLE   0x0000

POWERSTEP2_GEN_GATECFG1_WD_EN_ENABLE

#define POWERSTEP2_GEN_GATECFG1_WD_EN_ENABLE   0x0800

POWERSTEP2_GEN_GATECFG1_WD_EN_MASK

#define POWERSTEP2_GEN_GATECFG1_WD_EN_MASK   0x0800

POWERSTEP2_GEN_GATECFG2_DEF

#define POWERSTEP2_GEN_GATECFG2_DEF

Value:

                                                          ( POWERSTEP2_GEN_GATECFG2_TBLANK_375_NS | \
                                                          POWERSTEP2_GEN_GATECFG2_TDT_125_NS )

POWERSTEP2_GEN_GATECFG2_MASK

#define POWERSTEP2_GEN_GATECFG2_MASK   0xFF

POWERSTEP2_GEN_GATECFG2_TBLANK_1000_NS

#define POWERSTEP2_GEN_GATECFG2_TBLANK_1000_NS   0xE0

POWERSTEP2_GEN_GATECFG2_TBLANK_125_NS

#define POWERSTEP2_GEN_GATECFG2_TBLANK_125_NS   0x00

POWERSTEP2_GEN_GATECFG2_TBLANK_250_NS

#define POWERSTEP2_GEN_GATECFG2_TBLANK_250_NS   0x20

POWERSTEP2_GEN_GATECFG2_TBLANK_375_NS

#define POWERSTEP2_GEN_GATECFG2_TBLANK_375_NS   0x40

POWERSTEP2_GEN_GATECFG2_TBLANK_MASK

#define POWERSTEP2_GEN_GATECFG2_TBLANK_MASK   0xE0

POWERSTEP2_GEN_GATECFG2_TDT_125_NS

#define POWERSTEP2_GEN_GATECFG2_TDT_125_NS   0x00

POWERSTEP2_GEN_GATECFG2_TDT_250_NS

#define POWERSTEP2_GEN_GATECFG2_TDT_250_NS   0x01

POWERSTEP2_GEN_GATECFG2_TDT_4000_NS

#define POWERSTEP2_GEN_GATECFG2_TDT_4000_NS   0x1F

POWERSTEP2_GEN_GATECFG2_TDT_MASK

#define POWERSTEP2_GEN_GATECFG2_TDT_MASK   0x1F

POWERSTEP2_GEN_MARK_DEF

#define POWERSTEP2_GEN_MARK_DEF   ( POWERSTEP2_GEN_MARK_ZERO )

POWERSTEP2_GEN_MARK_MASK

#define POWERSTEP2_GEN_MARK_MASK   0x3FFFFFul

POWERSTEP2_GEN_MARK_ZERO

#define POWERSTEP2_GEN_MARK_ZERO   0x000000ul

POWERSTEP2_GEN_MAX_SPEED_15610_STEP_S

#define POWERSTEP2_GEN_MAX_SPEED_15610_STEP_S   0x03FF

POWERSTEP2_GEN_MAX_SPEED_15_25_STEP_S

#define POWERSTEP2_GEN_MAX_SPEED_15_25_STEP_S   0x0001

POWERSTEP2_GEN_MAX_SPEED_305_STEP_S

#define POWERSTEP2_GEN_MAX_SPEED_305_STEP_S   0x0014

POWERSTEP2_GEN_MAX_SPEED_30_5_STEP_S

#define POWERSTEP2_GEN_MAX_SPEED_30_5_STEP_S   0x0002

POWERSTEP2_GEN_MAX_SPEED_991_25_STEP_S

#define POWERSTEP2_GEN_MAX_SPEED_991_25_STEP_S   0x0041

POWERSTEP2_GEN_MAX_SPEED_DEF

#define POWERSTEP2_GEN_MAX_SPEED_DEF   ( POWERSTEP2_GEN_MAX_SPEED_305_STEP_S )

POWERSTEP2_GEN_MAX_SPEED_MASK

#define POWERSTEP2_GEN_MAX_SPEED_MASK   0x03FF

POWERSTEP2_GEN_MIN_SPEED_DEF

#define POWERSTEP2_GEN_MIN_SPEED_DEF

Value:

                                                          ( POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_LOW | \
                                                          POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_STEP_S )

POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_HIGH

#define POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_HIGH   0x1000

POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_LOW

#define POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_LOW   0x0000

POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_MASK

#define POWERSTEP2_GEN_MIN_SPEED_LSPD_OPT_MASK   0x1000

POWERSTEP2_GEN_MIN_SPEED_MASK

#define POWERSTEP2_GEN_MIN_SPEED_MASK   0x1FFF

POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_238_STEP_S

#define POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_238_STEP_S   0x0001

POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_476_STEP_S

#define POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_476_STEP_S   0x0002

POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_STEP_S

#define POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_0_STEP_S   0x0000

POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_2_38_STEP_S

#define POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_2_38_STEP_S   0x000A

POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_976_3_STEP_S

#define POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_976_3_STEP_S   0x0FFF

POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_MASK

#define POWERSTEP2_GEN_MIN_SPEED_MIN_SPEED_MASK   0x0FFF

POWERSTEP2_GEN_OCD_TH_1000_MV

#define POWERSTEP2_GEN_OCD_TH_1000_MV   0x1F

POWERSTEP2_GEN_OCD_TH_281_25_MV

#define POWERSTEP2_GEN_OCD_TH_281_25_MV   0x08

POWERSTEP2_GEN_OCD_TH_31_25_MV

#define POWERSTEP2_GEN_OCD_TH_31_25_MV   0x00

POWERSTEP2_GEN_OCD_TH_531_25_MV

#define POWERSTEP2_GEN_OCD_TH_531_25_MV   0x10

POWERSTEP2_GEN_OCD_TH_62_5_MV

#define POWERSTEP2_GEN_OCD_TH_62_5_MV   0x01

POWERSTEP2_GEN_OCD_TH_93_75_MV

#define POWERSTEP2_GEN_OCD_TH_93_75_MV   0x02

POWERSTEP2_GEN_OCD_TH_DEF

#define POWERSTEP2_GEN_OCD_TH_DEF   ( POWERSTEP2_GEN_OCD_TH_531_25_MV )

POWERSTEP2_GEN_OCD_TH_MASK

#define POWERSTEP2_GEN_OCD_TH_MASK   0x1F

POWERSTEP2_GEN_SPEED_MASK

#define POWERSTEP2_GEN_SPEED_MASK   0x0FFFFFul

POWERSTEP2_GEN_STATUS_BUSY_MASK

#define POWERSTEP2_GEN_STATUS_BUSY_MASK   0x0002

POWERSTEP2_GEN_STATUS_CMD_ERROR_MASK

#define POWERSTEP2_GEN_STATUS_CMD_ERROR_MASK   0x0080

POWERSTEP2_GEN_STATUS_DIR_MASK

#define POWERSTEP2_GEN_STATUS_DIR_MASK   0x0010

POWERSTEP2_GEN_STATUS_HIZ_MASK

#define POWERSTEP2_GEN_STATUS_HIZ_MASK   0x0001

POWERSTEP2_GEN_STATUS_MASK

#define POWERSTEP2_GEN_STATUS_MASK   0xFFFF

POWERSTEP2_GEN_STATUS_MOT_STATUS_MASK

#define POWERSTEP2_GEN_STATUS_MOT_STATUS_MASK   0x0060

POWERSTEP2_GEN_STATUS_OCD_MASK

#define POWERSTEP2_GEN_STATUS_OCD_MASK   0x2000

POWERSTEP2_GEN_STATUS_STALL_A_MASK

#define POWERSTEP2_GEN_STATUS_STALL_A_MASK   0x8000

POWERSTEP2_GEN_STATUS_STALL_B_MASK

#define POWERSTEP2_GEN_STATUS_STALL_B_MASK   0x4000

POWERSTEP2_GEN_STATUS_STCK_MOD_MASK

#define POWERSTEP2_GEN_STATUS_STCK_MOD_MASK   0x0100

POWERSTEP2_GEN_STATUS_SW_EVN_MASK

#define POWERSTEP2_GEN_STATUS_SW_EVN_MASK   0x0008

POWERSTEP2_GEN_STATUS_SW_F_MASK

#define POWERSTEP2_GEN_STATUS_SW_F_MASK   0x0004

POWERSTEP2_GEN_STATUS_TH_STATUS_MASK

#define POWERSTEP2_GEN_STATUS_TH_STATUS_MASK   0x1800

POWERSTEP2_GEN_STATUS_UVLO_ADC_MASK

#define POWERSTEP2_GEN_STATUS_UVLO_ADC_MASK   0x0400

POWERSTEP2_GEN_STATUS_UVLO_MASK

#define POWERSTEP2_GEN_STATUS_UVLO_MASK   0x0200

POWERSTEP2_GEN_STEP_MODE_CM_VM_CURRENT

#define POWERSTEP2_GEN_STEP_MODE_CM_VM_CURRENT   0x08

POWERSTEP2_GEN_STEP_MODE_CM_VM_MASK

#define POWERSTEP2_GEN_STEP_MODE_CM_VM_MASK   0x08

POWERSTEP2_GEN_STEP_MODE_CM_VM_VOLTAGE

#define POWERSTEP2_GEN_STEP_MODE_CM_VM_VOLTAGE   0x00

POWERSTEP2_GEN_STEP_MODE_DEF

#define POWERSTEP2_GEN_STEP_MODE_DEF

Value:

                                                          ( POWERSTEP2_GEN_STEP_MODE_SYNC_EN_DISABLE | \
                                                          POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_FULL_STEP | \
                                                          POWERSTEP2_GEN_STEP_MODE_CM_VM_VOLTAGE | \
                                                          POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_32 )

POWERSTEP2_GEN_STEP_MODE_MASK

#define POWERSTEP2_GEN_STEP_MODE_MASK   0xFF

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_128

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_128   0x07

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_16

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_16   0x04

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_32

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_32   0x05

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_64

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_64   0x06

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_8

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_1_OVER_8   0x03

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_FULL_STEP

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_FULL_STEP   0x00

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_HALF_STEP

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_HALF_STEP   0x01

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_MASK

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_MASK   0x07

POWERSTEP2_GEN_STEP_MODE_STEP_SEL_QUARTER_STEP

#define POWERSTEP2_GEN_STEP_MODE_STEP_SEL_QUARTER_STEP   0x02

POWERSTEP2_GEN_STEP_MODE_SYNC_EN_DISABLE

#define POWERSTEP2_GEN_STEP_MODE_SYNC_EN_DISABLE   0x00

POWERSTEP2_GEN_STEP_MODE_SYNC_EN_ENABLE

#define POWERSTEP2_GEN_STEP_MODE_SYNC_EN_ENABLE   0x80

POWERSTEP2_GEN_STEP_MODE_SYNC_EN_MASK

#define POWERSTEP2_GEN_STEP_MODE_SYNC_EN_MASK   0x80

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_128

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_128   0x70

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_16

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_16   0x40

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_32

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_32   0x50

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_64

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_64   0x60

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_8

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_1_OVER_8   0x30

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_FULL_STEP

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_FULL_STEP   0x00

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_HALF_STEP

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_HALF_STEP   0x10

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_MASK

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_MASK   0x70

POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_QUARTER_STEP

#define POWERSTEP2_GEN_STEP_MODE_SYNC_SEL_QUARTER_STEP   0x20

POWERSTEP2_MAX_SPEED_MAX

#define POWERSTEP2_MAX_SPEED_MAX   15610.0f

POWERSTEP2_MAX_SPEED_MIN

#define POWERSTEP2_MAX_SPEED_MIN   15.25f

POWERSTEP2_MAX_SPEED_STEP

#define POWERSTEP2_MAX_SPEED_STEP   15.25f

POWERSTEP2_MIN_SPEED_MAX

#define POWERSTEP2_MIN_SPEED_MAX   976.3f

POWERSTEP2_MIN_SPEED_MIN

#define POWERSTEP2_MIN_SPEED_MIN   0.0f

POWERSTEP2_MIN_SPEED_STEP

#define POWERSTEP2_MIN_SPEED_STEP   0.238f

Power Step 2 speed min and max settings.

Specified speed min and max settings in step/s of Power Step 2 Click driver.

POWERSTEP2_PIN_HIGH_LEVEL

#define POWERSTEP2_PIN_HIGH_LEVEL   1

POWERSTEP2_PIN_LOW_LEVEL

#define POWERSTEP2_PIN_LOW_LEVEL   0

Power Step 2 pin logic level setting.

Specified setting for pin logic level of Power Step 2 Click driver.

POWERSTEP2_ROUND_TO_INT

#define POWERSTEP2_ROUND_TO_INT   0.5f

Power Step 2 round to upper int settings.

Specified round to upper int settings of Power Step 2 Click driver.

POWERSTEP2_SET_DATA_SAMPLE_EDGE

#define POWERSTEP2_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note

Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with powerstep2_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

POWERSTEP2_SET_DATA_SAMPLE_MIDDLE

#define POWERSTEP2_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

POWERSTEP2_SPEED_FAST

#define POWERSTEP2_SPEED_FAST   3

POWERSTEP2_SPEED_MEDIUM

#define POWERSTEP2_SPEED_MEDIUM   2

POWERSTEP2_SPEED_SLOW

#define POWERSTEP2_SPEED_SLOW   1

POWERSTEP2_SPEED_VERY_FAST

#define POWERSTEP2_SPEED_VERY_FAST   4

POWERSTEP2_SPEED_VERY_SLOW

#define POWERSTEP2_SPEED_VERY_SLOW   0

Power Step 2 driving speed in step clock mode settings.

Specified setting for rotation speed in step clock mode.

POWERSTEP2_STEP_MODE_1_OVER_128

#define POWERSTEP2_STEP_MODE_1_OVER_128   7

POWERSTEP2_STEP_MODE_1_OVER_16

#define POWERSTEP2_STEP_MODE_1_OVER_16   4

POWERSTEP2_STEP_MODE_1_OVER_32

#define POWERSTEP2_STEP_MODE_1_OVER_32   5

POWERSTEP2_STEP_MODE_1_OVER_64

#define POWERSTEP2_STEP_MODE_1_OVER_64   6

POWERSTEP2_STEP_MODE_1_OVER_8

#define POWERSTEP2_STEP_MODE_1_OVER_8   3

POWERSTEP2_STEP_MODE_FULL_STEP

#define POWERSTEP2_STEP_MODE_FULL_STEP   0

Power Step 2 step mode setting.

Specified setting for step mode of Power Step 2 Click driver.

POWERSTEP2_STEP_MODE_HALF_STEP

#define POWERSTEP2_STEP_MODE_HALF_STEP   1

POWERSTEP2_STEP_MODE_QUARTER_STEP

#define POWERSTEP2_STEP_MODE_QUARTER_STEP   2

POWERSTEP2_V_CONFIG_DEF

#define POWERSTEP2_V_CONFIG_DEF

Value:

                                                          ( POWERSTEP2_V_CONFIG_F_PWM_INT_62_5_KHZ | \
                                                          POWERSTEP2_V_CONFIG_F_PWM_DEC_62_5_KHZ | \
                                                          POWERSTEP2_V_CONFIG_VCCVAL_15_V | \
                                                          POWERSTEP2_V_CONFIG_UVLOVAL_LOW | \
                                                          POWERSTEP2_V_CONFIG_OC_SD_DISABLE | \
                                                          POWERSTEP2_V_CONFIG_EN_VSCOMP_DISABLE | \
                                                          POWERSTEP2_V_CONFIG_SW_MODE_HARD_STOP_INT | \
                                                          POWERSTEP2_V_CONFIG_EXT_CLK_DISABLE | \
                                                          POWERSTEP2_V_CONFIG_OSC_SEL_INT_16_MHZ )

POWERSTEP2_V_CONFIG_EN_VSCOMP_DISABLE

#define POWERSTEP2_V_CONFIG_EN_VSCOMP_DISABLE   0x0000

POWERSTEP2_V_CONFIG_EN_VSCOMP_ENABLE

#define POWERSTEP2_V_CONFIG_EN_VSCOMP_ENABLE   0x0020

POWERSTEP2_V_CONFIG_EN_VSCOMP_MASK

#define POWERSTEP2_V_CONFIG_EN_VSCOMP_MASK   0x0020

POWERSTEP2_V_CONFIG_EXT_CLK_DISABLE

#define POWERSTEP2_V_CONFIG_EXT_CLK_DISABLE   0x0000

POWERSTEP2_V_CONFIG_EXT_CLK_ENABLE

#define POWERSTEP2_V_CONFIG_EXT_CLK_ENABLE   0x0008

POWERSTEP2_V_CONFIG_EXT_CLK_MASK

#define POWERSTEP2_V_CONFIG_EXT_CLK_MASK   0x0008

POWERSTEP2_V_CONFIG_F_PWM_DEC_19_5_KHZ

#define POWERSTEP2_V_CONFIG_F_PWM_DEC_19_5_KHZ   0x0000

POWERSTEP2_V_CONFIG_F_PWM_DEC_31_3_KHZ

#define POWERSTEP2_V_CONFIG_F_PWM_DEC_31_3_KHZ   0x0C00

POWERSTEP2_V_CONFIG_F_PWM_DEC_62_5_KHZ

#define POWERSTEP2_V_CONFIG_F_PWM_DEC_62_5_KHZ   0x1C00

POWERSTEP2_V_CONFIG_F_PWM_DEC_MASK

#define POWERSTEP2_V_CONFIG_F_PWM_DEC_MASK   0x1C00

POWERSTEP2_V_CONFIG_F_PWM_INT_19_5_KHZ

#define POWERSTEP2_V_CONFIG_F_PWM_INT_19_5_KHZ   0x0000

POWERSTEP2_V_CONFIG_F_PWM_INT_31_3_KHZ

#define POWERSTEP2_V_CONFIG_F_PWM_INT_31_3_KHZ   0x0000

POWERSTEP2_V_CONFIG_F_PWM_INT_62_5_KHZ

#define POWERSTEP2_V_CONFIG_F_PWM_INT_62_5_KHZ   0x0000

POWERSTEP2_V_CONFIG_F_PWM_INT_MASK

#define POWERSTEP2_V_CONFIG_F_PWM_INT_MASK   0xE000

POWERSTEP2_V_CONFIG_MASK

#define POWERSTEP2_V_CONFIG_MASK   0xFFFF

POWERSTEP2_V_CONFIG_OC_SD_DISABLE

#define POWERSTEP2_V_CONFIG_OC_SD_DISABLE   0x0000

POWERSTEP2_V_CONFIG_OC_SD_ENABLE

#define POWERSTEP2_V_CONFIG_OC_SD_ENABLE   0x0080

POWERSTEP2_V_CONFIG_OC_SD_MASK

#define POWERSTEP2_V_CONFIG_OC_SD_MASK   0x0080

POWERSTEP2_V_CONFIG_OSC_SEL_INT_16_MHZ

#define POWERSTEP2_V_CONFIG_OSC_SEL_INT_16_MHZ   0x0000

POWERSTEP2_V_CONFIG_OSC_SEL_MASK

#define POWERSTEP2_V_CONFIG_OSC_SEL_MASK   0x0007

POWERSTEP2_V_CONFIG_SW_MODE_HARD_STOP_INT

#define POWERSTEP2_V_CONFIG_SW_MODE_HARD_STOP_INT   0x0000

POWERSTEP2_V_CONFIG_SW_MODE_MASK

#define POWERSTEP2_V_CONFIG_SW_MODE_MASK   0x0010

POWERSTEP2_V_CONFIG_SW_MODE_USER_DISPOSAL

#define POWERSTEP2_V_CONFIG_SW_MODE_USER_DISPOSAL   0x0010

POWERSTEP2_V_CONFIG_UVLOVAL_HIGH

#define POWERSTEP2_V_CONFIG_UVLOVAL_HIGH   0x0100

POWERSTEP2_V_CONFIG_UVLOVAL_LOW

#define POWERSTEP2_V_CONFIG_UVLOVAL_LOW   0x0000

POWERSTEP2_V_CONFIG_UVLOVAL_MASK

#define POWERSTEP2_V_CONFIG_UVLOVAL_MASK   0x0100

POWERSTEP2_V_CONFIG_VCCVAL_15_V

#define POWERSTEP2_V_CONFIG_VCCVAL_15_V   0x0200

POWERSTEP2_V_CONFIG_VCCVAL_7_5_V

#define POWERSTEP2_V_CONFIG_VCCVAL_7_5_V   0x0000

POWERSTEP2_V_CONFIG_VCCVAL_MASK

#define POWERSTEP2_V_CONFIG_VCCVAL_MASK   0x0200

POWERSTEP2_V_FN_SLP_ACC_0

#define POWERSTEP2_V_FN_SLP_ACC_0   0x00

POWERSTEP2_V_FN_SLP_ACC_0_000015

#define POWERSTEP2_V_FN_SLP_ACC_0_000015   0x01

POWERSTEP2_V_FN_SLP_ACC_0_00003

#define POWERSTEP2_V_FN_SLP_ACC_0_00003   0x02

POWERSTEP2_V_FN_SLP_ACC_0_000135

#define POWERSTEP2_V_FN_SLP_ACC_0_000135   0x08

POWERSTEP2_V_FN_SLP_ACC_0_00063

#define POWERSTEP2_V_FN_SLP_ACC_0_00063   0x29

POWERSTEP2_V_FN_SLP_ACC_0_004

#define POWERSTEP2_V_FN_SLP_ACC_0_004   0xFF

POWERSTEP2_V_FN_SLP_ACC_DEF

#define POWERSTEP2_V_FN_SLP_ACC_DEF   ( POWERSTEP2_V_FN_SLP_ACC_0_00063 )

POWERSTEP2_V_FN_SLP_ACC_MASK

#define POWERSTEP2_V_FN_SLP_ACC_MASK   0xFF

POWERSTEP2_V_FN_SLP_DEC_0

#define POWERSTEP2_V_FN_SLP_DEC_0   0x00

POWERSTEP2_V_FN_SLP_DEC_0_000015

#define POWERSTEP2_V_FN_SLP_DEC_0_000015   0x01

POWERSTEP2_V_FN_SLP_DEC_0_00003

#define POWERSTEP2_V_FN_SLP_DEC_0_00003   0x02

POWERSTEP2_V_FN_SLP_DEC_0_000135

#define POWERSTEP2_V_FN_SLP_DEC_0_000135   0x08

POWERSTEP2_V_FN_SLP_DEC_0_00063

#define POWERSTEP2_V_FN_SLP_DEC_0_00063   0x29

POWERSTEP2_V_FN_SLP_DEC_0_004

#define POWERSTEP2_V_FN_SLP_DEC_0_004   0xFF

POWERSTEP2_V_FN_SLP_DEC_DEF

#define POWERSTEP2_V_FN_SLP_DEC_DEF   ( POWERSTEP2_V_FN_SLP_DEC_0_00063 )

POWERSTEP2_V_FN_SLP_DEC_MASK

#define POWERSTEP2_V_FN_SLP_DEC_MASK   0xFF

POWERSTEP2_V_INT_SPEED_0_0596_STEP_S

#define POWERSTEP2_V_INT_SPEED_0_0596_STEP_S   0x0001

POWERSTEP2_V_INT_SPEED_0_1192_STEP_S

#define POWERSTEP2_V_INT_SPEED_0_1192_STEP_S   0x0002

POWERSTEP2_V_INT_SPEED_0_STEP_S

#define POWERSTEP2_V_INT_SPEED_0_STEP_S   0x0000

POWERSTEP2_V_INT_SPEED_61_5668_STEP_S

#define POWERSTEP2_V_INT_SPEED_61_5668_STEP_S   0x0408

POWERSTEP2_V_INT_SPEED_976_5_STEP_S

#define POWERSTEP2_V_INT_SPEED_976_5_STEP_S   0x3FFF

POWERSTEP2_V_INT_SPEED_DEF

#define POWERSTEP2_V_INT_SPEED_DEF   ( POWERSTEP2_V_INT_SPEED_61_5668_STEP_S )

POWERSTEP2_V_INT_SPEED_MASK

#define POWERSTEP2_V_INT_SPEED_MASK   0x3FFF

POWERSTEP2_V_K_THERM_1

#define POWERSTEP2_V_K_THERM_1   0x00

POWERSTEP2_V_K_THERM_1_03125

#define POWERSTEP2_V_K_THERM_1_03125   0x01

POWERSTEP2_V_K_THERM_1_0625

#define POWERSTEP2_V_K_THERM_1_0625   0x02

POWERSTEP2_V_K_THERM_1_46875

#define POWERSTEP2_V_K_THERM_1_46875   0x0F

POWERSTEP2_V_K_THERM_DEF

#define POWERSTEP2_V_K_THERM_DEF   ( POWERSTEP2_V_K_THERM_1 )

POWERSTEP2_V_K_THERM_MASK

#define POWERSTEP2_V_K_THERM_MASK   0x0F

POWERSTEP2_V_KVAL_ACC_0_004_VS

#define POWERSTEP2_V_KVAL_ACC_0_004_VS   0x01

POWERSTEP2_V_KVAL_ACC_0_008_VS

#define POWERSTEP2_V_KVAL_ACC_0_008_VS   0x02

POWERSTEP2_V_KVAL_ACC_0_104_VS

#define POWERSTEP2_V_KVAL_ACC_0_104_VS   0x19

POWERSTEP2_V_KVAL_ACC_0_168_VS

#define POWERSTEP2_V_KVAL_ACC_0_168_VS   0x29

POWERSTEP2_V_KVAL_ACC_0_996_VS

#define POWERSTEP2_V_KVAL_ACC_0_996_VS   0xFF

POWERSTEP2_V_KVAL_ACC_0_VS

#define POWERSTEP2_V_KVAL_ACC_0_VS   0x00

POWERSTEP2_V_KVAL_ACC_DEF

#define POWERSTEP2_V_KVAL_ACC_DEF   ( POWERSTEP2_V_KVAL_ACC_0_168_VS )

POWERSTEP2_V_KVAL_ACC_MASK

#define POWERSTEP2_V_KVAL_ACC_MASK   0xFF

POWERSTEP2_V_KVAL_DEC_0_004_VS

#define POWERSTEP2_V_KVAL_DEC_0_004_VS   0x01

POWERSTEP2_V_KVAL_DEC_0_008_VS

#define POWERSTEP2_V_KVAL_DEC_0_008_VS   0x02

POWERSTEP2_V_KVAL_DEC_0_104_VS

#define POWERSTEP2_V_KVAL_DEC_0_104_VS   0x19

POWERSTEP2_V_KVAL_DEC_0_168_VS

#define POWERSTEP2_V_KVAL_DEC_0_168_VS   0x29

POWERSTEP2_V_KVAL_DEC_0_996_VS

#define POWERSTEP2_V_KVAL_DEC_0_996_VS   0xFF

POWERSTEP2_V_KVAL_DEC_0_VS

#define POWERSTEP2_V_KVAL_DEC_0_VS   0x00

POWERSTEP2_V_KVAL_DEC_DEF

#define POWERSTEP2_V_KVAL_DEC_DEF   ( POWERSTEP2_V_KVAL_DEC_0_168_VS )

POWERSTEP2_V_KVAL_DEC_MASK

#define POWERSTEP2_V_KVAL_DEC_MASK   0xFF

POWERSTEP2_V_KVAL_HOLD_0_004_VS

#define POWERSTEP2_V_KVAL_HOLD_0_004_VS   0x01

POWERSTEP2_V_KVAL_HOLD_0_008_VS

#define POWERSTEP2_V_KVAL_HOLD_0_008_VS   0x02

POWERSTEP2_V_KVAL_HOLD_0_104_VS

#define POWERSTEP2_V_KVAL_HOLD_0_104_VS   0x19

POWERSTEP2_V_KVAL_HOLD_0_168_VS

#define POWERSTEP2_V_KVAL_HOLD_0_168_VS   0x29

POWERSTEP2_V_KVAL_HOLD_0_996_VS

#define POWERSTEP2_V_KVAL_HOLD_0_996_VS   0xFF

POWERSTEP2_V_KVAL_HOLD_0_VS

#define POWERSTEP2_V_KVAL_HOLD_0_VS   0x00

POWERSTEP2_V_KVAL_HOLD_DEF

#define POWERSTEP2_V_KVAL_HOLD_DEF   ( POWERSTEP2_V_KVAL_HOLD_0_168_VS )

POWERSTEP2_V_KVAL_HOLD_MASK

#define POWERSTEP2_V_KVAL_HOLD_MASK   0xFF

POWERSTEP2_V_KVAL_RUN_0_004_VS

#define POWERSTEP2_V_KVAL_RUN_0_004_VS   0x01

POWERSTEP2_V_KVAL_RUN_0_008_VS

#define POWERSTEP2_V_KVAL_RUN_0_008_VS   0x02

POWERSTEP2_V_KVAL_RUN_0_104_VS

#define POWERSTEP2_V_KVAL_RUN_0_104_VS   0x19

POWERSTEP2_V_KVAL_RUN_0_168_VS

#define POWERSTEP2_V_KVAL_RUN_0_168_VS   0x29

POWERSTEP2_V_KVAL_RUN_0_996_VS

#define POWERSTEP2_V_KVAL_RUN_0_996_VS   0xFF

POWERSTEP2_V_KVAL_RUN_0_VS

#define POWERSTEP2_V_KVAL_RUN_0_VS   0x00

POWERSTEP2_V_KVAL_RUN_DEF

#define POWERSTEP2_V_KVAL_RUN_DEF   ( POWERSTEP2_V_KVAL_RUN_0_168_VS )

POWERSTEP2_V_KVAL_RUN_MASK

#define POWERSTEP2_V_KVAL_RUN_MASK   0xFF

POWERSTEP2_V_ST_SLP_0

#define POWERSTEP2_V_ST_SLP_0   0x00

POWERSTEP2_V_ST_SLP_0_000015

#define POWERSTEP2_V_ST_SLP_0_000015   0x01

POWERSTEP2_V_ST_SLP_0_00003

#define POWERSTEP2_V_ST_SLP_0_00003   0x02

POWERSTEP2_V_ST_SLP_0_000135

#define POWERSTEP2_V_ST_SLP_0_000135   0x08

POWERSTEP2_V_ST_SLP_0_004

#define POWERSTEP2_V_ST_SLP_0_004   0xFF

POWERSTEP2_V_ST_SLP_DEF

#define POWERSTEP2_V_ST_SLP_DEF   ( POWERSTEP2_V_ST_SLP_0_000135 )

POWERSTEP2_V_ST_SLP_MASK

#define POWERSTEP2_V_ST_SLP_MASK   0xFF

POWERSTEP2_V_STALL_TH_1000_MV

#define POWERSTEP2_V_STALL_TH_1000_MV   0x1F

POWERSTEP2_V_STALL_TH_281_25_MV

#define POWERSTEP2_V_STALL_TH_281_25_MV   0x08

POWERSTEP2_V_STALL_TH_31_25_MV

#define POWERSTEP2_V_STALL_TH_31_25_MV   0x00

POWERSTEP2_V_STALL_TH_531_25_MV

#define POWERSTEP2_V_STALL_TH_531_25_MV   0x10

POWERSTEP2_V_STALL_TH_62_5_MV

#define POWERSTEP2_V_STALL_TH_62_5_MV   0x01

POWERSTEP2_V_STALL_TH_93_75_MV

#define POWERSTEP2_V_STALL_TH_93_75_MV   0x02

POWERSTEP2_V_STALL_TH_DEF

#define POWERSTEP2_V_STALL_TH_DEF   ( POWERSTEP2_V_STALL_TH_531_25_MV )

POWERSTEP2_V_STALL_TH_MASK

#define POWERSTEP2_V_STALL_TH_MASK   0x1F